1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a stack type semiconductor device and a method of fabricating and testing the same.
2. Related Art
In general, a stack type semiconductor device refers to a structure in which a plurality of dies in which semiconductor circuits is designed. The stack dies are electrically coupled through a Through Silicon Via (TSV).
The TSV fabrication methods may be classified into a via-first, a via-middle, and a via-last method based on when the TSV is fabricated. The via-last method may be subdivided into a via-front method and a via-backside method.
In the via-first, via-middle, and via-front methods, vias are formed in specific positions of a semiconductor substrate, and the vias are exposed on the back surface of the semiconductor substrate by a back-grinding process.
In this stack type semiconductor device, after fabricating the dies or after the dies are stacked, a test is performed to determine whether the vias are bad.
In particular, in order to perform the via test in semiconductor dies formed using the via-first, via-middle, or via-front method, back-grinding must be performed on the semiconductor dies so that vias are exposed on the back of the semiconductor substrate. Next, whether the vias are bad or not is checked by testing the back-grinded semiconductor dies one by one or by performing a test after stacking the semiconductor dies.
In order to perform a test on each of the semiconductor dies by screening after back-grinding, specific patterns are formed in the back of the semiconductor substrate, that is, a grinded face, and the vias are interconnected through specific patterns.
If specific patterns are formed in the back of the semiconductor substrate in order to perform a test, however, a crack may be generated in a wafer when the test is performed and there are difficulties in forming the patterns while avoiding a phenomenon in which the thinned wafer is rolled because the semiconductor substrate has become thin by back-grinding. Furthermore, there are problems in that an additional process of removing the patterns formed for the test is required after the test is completed and the wafer may be damaged in the process of removing the patterns. Moreover, a test in the vias coupled by the test patterns is possible, but a test in circuit patterns formed in a core region is not possible.
A Boundary Scan Test (BST) method may be used in order to perform a test after stacking individual dies. However, all dies including bad vias cannot be precisely screened by using the BST method. If packaging is performed in the state in which a die includes a bad via, the yield cannot be secured.